1. Field of the Invention
The present invention relates to a dynamic random access memory having improved capability for accessing memory cells located along a common row.
2. Description of the Prior Art
A dynamic random access memory (DRAM) comprises individual memory locations, referred to as "cells", arranged in an array of rows and columns. A given memory cell is located in the vicinity of the intersection of a row conductor and a column conductor. The cell is "accessed" to perform a data read or write operation when the corresponding row and column conductors are activated. Referring to FIG. 1, a typical DRAM design utilizes a row decoder to select a given row by placing a voltage thereon, which is positive in the case of n-channel field effect access transistors. This row conductor voltage allows all of the access transistors in the selected row to conduct charge between an information storage capacitor and the column conductor associated with each selected cell. Similarly, a column decoder is utilized to select a given column of memory cells for connection to data output (DQ and DQ) lines.
For example, if row R1 and column conductor C1 are selected, then data may be written (stored) or read (retrieved) from capacitor 11 by conduction through access transistor M11. Note that a given column conductor (e.g., C1) typically has associated with it a complement column conductor (e.g., C1) that is also selected for the given column. The complement column conductor provides a reference voltage during read operations so that the sense amplifier for the selected column (e.g., sense amp 1) can rapidly determine whether a high voltage, referred to as a "1", or a low voltage, referred to as a "0", is stored in the selected memory cell. The column functions are interchangeable, so that C1 may be selected to read a given cell (e.g., M21-21), with C1 then serving as its complement conductor, as when row conductor R2 is selected. The selected column conductor (e.g., C1) communicates the data to the DQ line, and the selected complement column conductor (e.g., CI) communicates the complement data to the DQ line. The Q buffer then provides valid data output when a strobe signal (CQL) is present, assuming the Q buffer is not placed in the "tristate" condition by a high level on CE or the clock early write (CEW) signal.
In order to select the desired row and column, address bits are supplied to the row and column decoders. For example, to select one row out of 256 rows, 8 address bits (A1 . . . A8) are supplied to the row decoder, since 2.sup.8 =256. Similarly, to select one of 256 columns, 8 other address bits (A9 . . . A16) are supplied to the column decoder. This provides access to any one of 256.times.256=65,536 memory cells. Other array sizes may be provided for by using different numbers of address bits.
In typical DRAMs, the address bits are time multiplexed into two groups, with the row address bits being applied first to the address terminals, and then the column address bits. In this way, the number of integrated circuit terminals can be reduced. For example, the exemplary array of FIG. 1 needs only 8 address terminals when thus multiplexed, instead of 16. To accomplish this address multiplex function, the first group of 8 bits (row bits A1 . . . A8) are placed on the address terminals by the circuitry requesting memory access, and then latched into the row decoder by a "row enable" signal, RE, also referred to as "row access strobe", RAS, in the art. Next, the column bits (A9-A16) are placed on the address terminals, and latched into the column decoder by a "column enable" signal, CE, also known as the "column access strobe", CAS, in the art. After a short delay, referred to as the "access time" (T.sub.ACC), the desired memory cell is selected, and in the case of a read operation, the stored data appears on the DQ line (and its complement on the DQ line). This sequence of operations is illustrated in FIG. 2. Note that the row and column address bits are maintained valid for the times indicated on the "ADR" graph, and similarly for the data bits on the "Q" graph.
In one conventional mode of memory operation, the RE signal is again applied (e.g., a high to low transition), followed by the CE signal, when the next memory data bit (e.g., data bit 2) is to be accessed for a read operation. This data bit 2 assumes a high or low voltage level, depending upon whether a "1" or "0" is stored at the selected location, during a second period of valid data time. However, note that the first and second valid data periods are separated by a minimum time interval, T.sub.INV, when the data output is invalid. This is accomplished by allowing the Q output of the Q buffer to assume a high impedance state, referred to as the "tristate" condition. The tristate condition effectively disconnects the Q output, and hence the data input/output (I/O) terminal of the memory, from the memory array information.
The purpose of the tristate interval is to allow two or more memory arrays, typically implemented on separate integrated circuit chips, to connect via a common input/output conductor, referred to as a "data bus"; see FIG. 3. Then, when one of the memories, for example memory 1, is providing a valid data output in response to an access request, the other memories connected to the bus (memories 2 . . . N) are in the tristate condition. This ensures that these other memories do not interfere with the accessed memory. Such interference could occur, for example, if memory 1 was providing a "1" data bit to the data bus, and another of the memories was providing a "0" data bit. During the next memory cycle, another of the memories, say memory 2, may be selected to provide the data output, with the other memories then being placed in the tristate condition. Note that which of the memories is providing the valid data, and which of the other memories are in the tristate condition, can be controlled by the individual CE signal applied thereto, since a high CE signal places a given memory in the tristate condition in a typical memory design.
Other modes of memory operation have also been utilized, generally in an attempt to reduce the time to access a desired memory location. For example, the above-noted address multiplex scheme requires twice as much time to input the necessary address bits than if both row and column address bits were presented simultaneously to the memory, as is the case with most static memory designs. Various schemes have been used to reduce this time penalty. In particular, the "page mode" scheme allows any of the memory cells along a selected row to be accessed by simply supplying the desired column address and the CE signal to the memory for each data access request. That is, the row address and the RE signal is supplied only once, as long as the desired memory cells are located in the selected row. Hence, a significant time saving can be achieved. However, prior art page mode schemes have retained the tristate period between valid data output periods.
A more recent "static column" technique is somewhat similar to page mode, except that even the column enable (CE) signals are not required when accessing cells located along a selected row. Rather, the column address bits themselves (e.g., A9-A16 above) are detected by means of transition detectors, which then select a new column when these bits are changed. That technique eliminates the tristate period, since a new cell provides valid output data (allowing for an unavoidable transition period) as soon as it is selected by a new address. However, the column address bits then must be maintained valid on the address terminals at least as long as valid output data is desired.
Another technique, referred to as "ripple mode", is similar to page mode, with one significant difference being that the column address bits begin to flow into the (static) column decoders when the CE signal goes high. Then, the addresses are latched into the address buffers when CE goes low. This technique allows somewhat greater latitude in the available time window between the RE low and CE low signals; see "C-MOS 256-K RAM with Wideband Output Stands by on Microwatts", A. Mohsen et al, Electronics, June 14, 1984, pp. 138-143. (In contrast, in page mode the column address bits must be valid when CE goes low, and for a fixed hold time thereafter. This allows the column decoder time to sample and latch the column addresses.)
Still another addressing technique, referred to as "nibble mode", provides four data output bits when a given memory location is specified. The four bits are time-multiplexed onto a single I/O terminal, and the data remains valid (except for transition times) during the four-bit output period. However, the output is then tristated when a new location is specified. Furthermore, the four data bits are typically not all obtained from the same row of memory cells per access request.